ADV7390 Datasheet, PDF (1/96 Pages) Analog Devices – Low Power, Chip Scale 10-Bit SD/HD Video Encoder

Low Power, Chip Scale
10-Bit SD/HD Video Encoder
ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
3 high quality, 10-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y/C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Advanced power management
Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Serial MPU interface with dual I²C® and SPI® compatibility
2.7 V or 3.3 V analog operation
1.8 V digital operation
3.3 V I/O operation
Temperature range: −40°C to +85°C
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
APPLICATIONS
Mobile handsets
Digital still cameras
Portable media and DVD players
Portable game consoles
Digital camcorders
Set-top box (STB)
Automotive infotainment (ADV7393 only)
FUNCTIONAL BLOCK DIAGRAM
DGND (2)
V_DD (2)
SCL/ SDA/ ^ALSB/
MOSI SCLK SPI_SS
SFL/
MISO
AGND VAA
GND_IO
VDD_IO
P15 TO P0/
P7 TO P0
VBI DATA SERVICE
INSERTION
4:2:2 TO 4:4:4
INPUT
DEINTERLEAVE
RGB/YCrCb
TO
YUV
MATRIX
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
ADV739x
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
10-BIT
DAC 1
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
YUV
TO
YCrCb/
RGB
16×
FILTER
10-BIT
DAC 2
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
10-BIT
DAC 3
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
TO
RGB MATRIX
4×
FILTER
DAC 1
DAC 2
DAC 3
POWER
MANAGEMENT
CONTROL
VIDEO TIMING GENERATOR
16x/4x OVERSAMPLING PLL
REFERENCE
AND CABLE
DETECT
R_SET
RESET
HSYNC
VSYNC
Figure 1.
CLKIN PV_DD PGND EXT_LF
COMP
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098, and other intellectual property rights.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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