ADUM4135 Datasheet, PDF (1/17 Pages) Analog Devices – Single-/Dual-Supply, High Voltage Isolated IGBT Gate Driver with Miller Clamp

Data Sheet
Single-/Dual-Supply, High Voltage Isolated
IGBT Gate Driver with Miller Clamp
ADuM4135
FEATURES
GENERAL DESCRIPTION
4 A peak drive output capability
Output power device resistance: <1 Ω
Desaturation protection
Isolated desaturation fault reporting
Soft shutdown on fault
Miller clamp output with gate sense input
Isolated fault and ready functions
Low propagation delay: 55 ns typical
Minimum pulse width: 50 ns
The ADuM4135 is a single-channel gate driver specifically
optimized for driving insulated gate bipolar transistors (IGBTs).
Analog Devices, Inc., iCoupler® technology provides isolation
between the input signal and the output gate drive.
The ADuM4135 includes a Miller clamp to provide robust
IGBT turn-off with a single-rail supply when the gate voltage
drops below 2 V. Operation with unipolar or bipolar secondary
supplies is possible, with or without the Miller clamp operation.
Operating temperature range: −40°C to +125°C
The Analog Devices chip scale transformers also provide
Output voltage range to 30 V
isolated communication of control information between the
Input voltage range from 2.3 V to 6 V
high voltage and low voltage domains of the chip. Information
Output and input undervoltage lockout (UVLO)
on the status of the chip can be read back from dedicated
Creepage distance: 7.8 mm minimum
100 kV/µs common-mode transient immunity (CMTI)
20 year lifetime for 600 V rms or 1092 V dc working voltage
Safety and regulatory approvals (pending)
5 kV ac for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak (reinforced/basic)
APPLICATIONS
outputs. Control of resetting the device after a fault on the
secondary is performed on the primary side of the device.
Integrated onto the ADuM4135 is a desaturation detection
circuit that provides protection against high voltage short-
circuit IGBT operation. The desaturation protection contains
noise reducing features such as a 300 ns masking time after a
switching event to mask voltage spikes due to initial turn-on.
An internal 500 µA current source allows low device count,
while the internal blanking switch allows the addition of an
MOSFET/IGBT gate drivers
external current source if more noise immunity is needed.
PV inverters
Motor drives
Power supplies
The secondary UVLO is set to 11 V with common IGBT
threshold levels taken into consideration.
FUNCTIONAL BLOCK DIAGRAM
V_SS1 1
1
V_I+ 2
V_I– 3
READY 4
1
FAULT 5
ADuM4135
UVLO
MASTER
LOGIC
PRIMARY
ENCODE
RESET 6
V_DD1 7
V_SS1 8
1
1
1
DECODE
NOTES
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE
ISOLATED FROM EACH OTHER.
TSD
CLAMP
LOGIC
2V
2
DECODE
ENCODE
MASTER
LOGIC
SECONDARY
2
9V
2
UVLO
16 V_SS2
2
15 GATE_SENSE
14 V_{OUT_ON}
13 V_DD2
12 V_{OUT_OFF}
11 GND₂
10 DESAT
9 V_SS2
2
Figure 1.
Rev. A
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