ADSP-BF539_15 Datasheet, PDF (1/60 Pages) Analog Devices – Blackfin Embedded Processor

FEATURES
Up to 533 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages; see Operating Conditions
on Page 26
Qualified for automotive applications
Programmable on-chip voltage regulator
316-ball Pb-free CSP_BGA package
MEMORY
148K bytes of on-chip memory
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
Optional 8M bit parallel flash with boot option
Memory management unit providing memory protection
Blackfin
Embedded Processor
ADSP-BF539/ADSP-BF539F
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and external
memory
PERIPHERALS
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
4 dual-channel, full-duplex synchronous serial ports,
supporting 16 stereo I²S channels
2 DMA controllers supporting 26 peripheral DMAs
4 memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
Media transceiver (MXVR) for connection
to a MOST network
3 SPI-compatible ports
Three 32-bit timer/counters with PWM support
3 UARTs with support for IrDA
2 TWI controllers compatible with I²C industry standard
Up to 38 general-purpose I/O pins (GPIO)
Up to 16 general-purpose flag pins (GPF)
Real-time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
GPIO
PORT
C
GPIO
PORT
D
GPIO
PORT
E
TWI0-1
CAN 2.0B
MXVR
SPI1-2
UART1-2
SPORT2-3
B
INTERRUPT
CONTROLLER
DMA CORE
BUS 2
DMA
CONTROLLER1
L1 INSTRUCTION
MEMORY
L1 DATA
MEMORY
DMA
CONTROLLER 0
DMA CORE
BUS 1
DMA
EXTERNAL
BUS 1
DMA CORE BUS 0
DMA
EXTERNAL
BUS 0
EXTERNAL PORT
FLASH, SDRAM CONTROL
WATCHDOG
TIMER
RTC
PPI
TIMER0-2
SPI0
UART0
SPORT0-1
GPIO
PORT
F
16
8M BIT PARALLEL FLASH
(See Table 1)
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. F
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