ADSP-BF538 Datasheet, PDF (1/56 Pages) Analog Devices – Blackfin Embedded Processor

a
Preliminary Technical Data
FEATURES
Up to 500 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core V_DD with on-chip voltage regulation
3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K bytes or 1M byte of flash memory (ADSP-BF538F parts
only)
Four dual-channel memory DMA controllers
Blackfin^®
Embedded Processor
ADSP-BF538/ADSP-BF538F
Memory management unit providing memory protection
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI^® and external
memory
PERIPHERALS
Parallel peripheral interface (PPI/GPIO)
supporting ITU-R 656 video data formats
Four dual-channel, full-duplex synchronous serial ports, sup-
porting 16 stereo I²S^® channels
Two DMA controllers supporting 26 DMA channels
Controller area network (CAN) 2.0B controller
Three SPI-compatible ports
Three timer/counters with PWM support
Three UARTs with support for IrDA^®
Two TWI controllers compatible with I²C^® industry standard
Up to 54 general-purpose I/O pins (GPIO)
Real time clock, watchdog timer, and core timer
On-chip PLL capable of 0.5x To 64x frequency multiplication
Debug/JTAG interface
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
GPIO
PORT
C
GPIO
PORT
D
GPIO
PORT
E
TWI0-1
CAN 2.0B
GPIO
SPI1-2
UART1-2
SPORT2-3
B
INTERRUPT
CONTROLLER
L1
INSTRUCTION
MEMORY
DMA ACCESS DMA CORE
BUS 1
BUS 1
L1
DATA
MEMORY
DMA CORE
BUS 0
DMA ACCESS
BUS 0
DMA
CONTROLLER1
EXTERNAL PORT
FLASH, SDRAM CONTROL
DMA
CONTROLLER0
DMA
E XTERNAL
BUS 1
DMA
EXTERNAL
BUS 0
512 KB OR 1 MB
FLASH MEMORY
(ADSP-BF538F ONLY)
BOOT ROM
WATCHDOG
TIMER
RTC
PPI
TIMER0-2
SPI0
UART0
SPORT0-1
GPIO
PORT
F
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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