ADSP-BF537_15 Datasheet, PDF (1/68 Pages) Analog Devices – Blackfin Embedded Processor

Blackfin
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see Operating Conditions
on Page 23)
Qualified for Automotive Applications (see Automotive Prod-
ucts on Page 66)
Programmable on-chip voltage regulator
182-ball and 208-ball CSP_BGA packages
MEMORY
Up to 132K bytes of on-chip memory
Instruction SRAM/cache and instruction SRAM
Data SRAM/cache plus additional dedicated data SRAM
Scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only)
Controller area network (CAN) 2.0B interface
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I²S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 32 interrupt inputs
Serial peripheral interface (SPI) compatible
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timer/counters with PWM support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), 8 with high current drivers
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
B
INTERRUPT
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA
CONTROLLER
EXTERNAL ACCESS BUS
DMA CORE BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
BOOT ROM
WATCHDOG TIMER
RTC
CAN
TWI
SPORT0
SPORT1
PPI
UART0-1
SPI
TIMER7-0
ETHERNET MAC
(See Table 1)
PORT J
GPIO
PORT G
GPIO
PORT F
GPIO
PORT H
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. J
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