ADSP-2185 Datasheet, PDF (1/32 Pages) Analog Devices – DSP Microcomputer

a
DSP Microcomputer
ADSP-2185
FEATURES
PERFORMANCE
30 ns Instruction Cycle Time 33 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM and
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables & Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe & Separate I/O Memory
Space Permits “Glueless” System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
*ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
16k ؋ 24
PROGRAM
MEMORY
16k ؋ 16
DATA
MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
TIMER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™* Emulator Interface Supports Debugging
in Final Systems
GENERAL NOTE
This data sheet represents production grade specifications for
the ADSP-2185 (5 V).
GENERAL DESCRIPTION
The ADSP-2185 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2185 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2185 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2185 is available in 100-pin TQFP package.
In addition, the ADSP-2185 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
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© Analog Devices, Inc., 1997