ADSP-21368 Datasheet, PDF (1/48 Pages) Analog Devices – Preliminary Technical Data

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Preliminary Technical Data
SHARC^® Processor
ADSP-21368
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby
headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,
MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and Multi-
channel encoder. Functions like Bass management, Delay,
Speaker equalization, Graphic equalization, Decoder/post-
processor algorithm combination support will vary
depending upon the chip version and the system configu-
rations. Please visit www.analog.com
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—2M bit of on-chip SRAM and a dedicated
6M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21368 is available with a 400 MHz core instruction
rate with unique audio centric peripherals such as the Digi-
tal Audio Interface, S/PDIF transceiver, serial ports, 8-
channel asynchronous sample rate converter, precision
clock generators and more. For complete ordering infor-
mation, see Ordering Guide on page 46
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
PROCESSING
EL EMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
4 BLOCKS OF
ON-CHIP MEMORY
2MBIT RAM, 6M BIT ROM
ADDR DATA
JTAG TEST & EMULATION
EXTERNAL PORT
8
SDRAM
CONTROLLER
ASYNCHRONOUS
3
MEMORY
INTERFACE
7
MULTIPROCESSOR
INTERFACE
24
ADDRESS
18
CONTROL
32
DATA
IOA(24)
IOD(32)
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, & DATA BUFFERS
32 PM ADDRESS BUS
32 DMADDRESS BUS
64 PM DATA BUS
64 DM DATA BUS
DMA
CONTROLLER
34 CHANNELS
MEMORY-T O-
MEMORY DMA (2)
PWM (16)
4 _{GPIO FLAGS/}
IRQ/TIMEXP
S
PRECISION CLOCK
GENERATORS (4)
SRC (8 CHANNELS)
SPDIF (RX/TX)
SERIAL PORTS (8)
INPUT DATA PORT/
PDAP
DAI PINS
DIGITAL AUDIO INTERFACE
20
SPI PORT (2)
TWO WIRE
INTERFACE
DPI PINS
UART (2)
TIMERS (3)
DIGITAL PERIPHERAL INTERFACE
I/O PROCESSOR
14
Figure 1. Functional Block Diagram – Processor Core
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Rev. PrA
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