ADSP-21266 Datasheet, PDF (1/44 Pages) Analog Devices – SHARC Embedded Processor

SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
The ADSP-21266 processes high performance audio while
enabling low system costs
Audio decoders and post processor algorithms support:
Nonvolatile memory can be configured to contain a combi-
nation of PCM 96 kHz, Dolby^® Digital, Dolby Digital
Surround EX^TM, DTS-ES^TM Discrete 6.1, DTS-ES Matrix 6.1,
DTS^® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-
PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and
DTS Neo:6^TM
Various multichannel surround-sound decoders are con-
tained in ROM. For configurations of decoder algorithms,
see Table 2 on Page 6.
SHARC^®
Embedded Processor
ADSP-21266
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI^® port, six serial
ports, a digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
The ADSP-21266 is available with a 150 MHz or a 200 MHz
core instruction rate. For complete ordering information,
see Ordering Guide on Page 44.
CORE PROCESSOR
TIME R
INSTRUCTION
CACHE
32 ؋ 48-BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 32
PROG RAM
SEQ UENCER
DUAL PORTED MEMORY
BLOCK 0
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
DUAL PORTED MEMORY
BLO CK 1
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
32
PM ADDRESS BUS
32
DM ADDRESS BUS
PROCES SING
ELEMENT
( PEX )
PRO CESSING
ELEMENT
( PE Y)
PX REGI STER
64 PM DATA BUS
64 DM DATA BUS
DMA CONTRO LLER
2 2 C HA N N ELS
4
SPI PORT (1)
6
JTAG TEST & EMULATION
S
SERIAL PORTS (6)
20
SI GNAL
RO UTI NG
UNI T
I NP UT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
PRECISION CLOCK
GENERATORS (2)
3
TIMERS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
I OD
IOA
( 32 )
( 18 )
4
GPIO FLAGS/
IRQ /TIMEXP
IOP
RE GISTE RS
(MEMORY MAPPED)
CO NTROL,
S TATUS ,
DATA BUFFERS
16
AD D R ES S/
D A TA BU S / GPIO
3
CON TR OL/GPIO
P ARALLEL
P ORT
Figure 1. Functional Block Diagram
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