ADSP-21262_05 Datasheet, PDF (1/48 Pages) Analog Devices – Embedded Processor

a
SUMMARY
High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI^® port, six serial
ports, a digital applications interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) that includes a parallel data acquisi-
tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—2M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
The ADSP-21262 is available in commercial and industrial
temperature grades. For complete ordering information,
see Ordering Guide on Page 46.
SHARC^®
Embedded Processor
ADSP-21262
KEY FEATURES
Serial ports offer left-justified sample-pair and I²S support
via 12 programmable and simultaneous receive or trans-
mit pins, which support up to 24 transmit or 24 receive I²S
channels of audio when all six serial ports (SPORTs) are
enabled or six full duplex TDM streams of up to 128
channels per frame
At 200 MHz (5 ns) core instruction rate, the ADSP-21262
operates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed- or floating-point
data
400 MMACS sustained performance at 200 MHz
Super Harvard Architecture—three independent buses for
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
Transfers between memory and core at up to four 32-bit
floating- or fixed-point words per cycle, sustained
2.4G byte/s bandwidth at 200 MHz core instruction rate
and 900M byte/sec is available via DMA
CORE PROCESSOR
TIME R
INSTRUCTION
CACHE
32 ؋ 48-BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 32
PROG RAM
SEQ UENCER
DUAL PORTED MEMORY
BLOCK 0
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
DUAL PORTED MEMORY
BLO CK 1
S RAM
1M BIT
ROM
2M BIT
ADDR
DATA
32
PM ADDRESS BUS
32
DM ADDRESS BUS
PROCES SING
ELEMENT
( PEX )
PRO CESSING
ELEMENT
( PE Y)
PX REGI STER
64 PM DATA BUS
64 DM DATA BUS
DMA CONTRO LLER
2 2 C HA N N ELS
4
SPI PORT (1)
6
JTAG TEST & EMULATION
S
SERIAL PORTS (6)
20
SI GNAL
RO UTI NG
UNI T
I NP UT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
PRECISION CLOCK
GENERATORS (2)
3
TIMERS (3)
I OD
IOA
( 32 )
( 18 )
4
GPIO FLAGS/
IRQ /TIMEXP
IOP
RE GISTE RS
(MEMORY MAPPED)
CO NTROL,
S TATUS ,
DATA BUFFERS
16
AD D R ES S/
D A TA BU S / GPIO
3
CON TR OL/GPIO
P ARALLEL
P ORT
DIGITAL APPLICATIONS INTERFACE
I/O PROCESSOR
Figure 1. Functional Block Diagram
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Rev. B
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