ADSP-21160M Datasheet, PDF (1/52 Pages) Analog Devices – DSP Microcomputer

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SHARC^®
DSP Microcomputer
ADSP-21160M
SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards-Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor,
4 M Bit On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURES
80 MHz (12.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
480 MFLOPS Peak and 320 MFLOPS Sustained
Performance (Based on FIR)
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and
On-Chip Emulation
400-Ball 27 ؋ 27 mm Metric PBGA Package
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