ADF4355 Datasheet, PDF (1/36 Pages) Analog Devices – Analog and digital lock detect

Data Sheet
Microwave Wideband Synthesizer
with Integrated VCO
ADF4355
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 6800 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 38-bit modulus
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
The ADF4355 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
when used with an external loop filter and an external reference
frequency. A series of frequency dividers permits operation
from 54 MHz to 6800 MHz.
The ADF4355 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate radio frequency
(RF) output frequencies as low as 54 MHz. For applications that
require isolation, the RF output stage can be muted. The mute
function is both pin and software controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF4355 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4355 also contains
hardware and software power-down modes.
FUNCTIONAL BLOCK DIAGRAM
CE
AV_DD
DV_DD
V_P
R_SET V_VCO
V_RF
AV_DD
REF_INA
REF_IN B
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REGISTER REGISTER REGISTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
÷116/2//342//864
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
C_REG1
C_REG2
CP_OUT
V_TUNE
V_REF
V_BIAS
V_REGVCO
RF_OUTA+
RF_OUTA–
PDB_RF
RF_OUTB+
RF_OUTB–
A_GND
CP_GND
A_GNDRF
Figure 1.
MULTIPLEXER
SD_GND A_GNDVCO
ADF4355
Rev. A
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