ADF4251 Datasheet, PDF (1/28 Pages) Analog Devices – Dual Fractional-N/Integer-N Frequency Synthesizer

Dual Fractional-N/Integer-N
Frequency Synthesizer
ADF4251
FEATURES
3.0 GHz Fractional-N/1.2 GHz Integer-N
2.7 V to 3.3 V Power Supply
Separate V_P Allows Extended Tuning Voltage to 5 V
Programmable Dual Modulus Prescaler
RF: 4/5, 8/9
IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Programmable Modulus on Fractional-N Synthesizer
Trade-Off Noise versus Spurious Performance
Software and Hardware Power-Down
APPLICATIONS
Base Stations for Mobile Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA,
PHS)
Wireless LANs
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4251 is a dual fractional-N/integer-N frequency
synthesizer that can be used to implement local oscillators
(LO) in the upconversion and downconversion sections of
wireless receivers and transmitters. Both the RF and IF syn-
thesizers consist of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a programmable refer-
ence divider. The RF synthesizer has a ⌺-⌬ based fractional
interpolator that allows programmable fractional-N division.
The IF synthesizer has programmable integer-N counters. A
complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and VCO (volt-
age controlled oscillator).
Control of all the on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
ADF4251
REF_IN
V_DD1 V_DD2 V_DD3 DV_DD V_P1
V_P2
؋2
DOUBLER
4-BIT R
COUNTER
PHASE
FREQUENCY
DETECTOR
R_SET
REFERENCE
CHARGE
PUMP
CE
CP_RF
MUXOUT
CLK
DATA
LE
FROM
REFIN
OUTPUT
MUX
24-BIT
DATA
REGISTER
؋2
DOUBLER
LOCK
DETECT
FRACTIONAL N
RF DIVIDER
INTEGER N
IF DIVIDER
15-BIT R
COUNTER
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
RF_INA
RF_INB
IF_INB
IF_INA
CP_IF
A_GND1 A_GND2 D_GND CP_GND1 CP_GND2
REV. 0
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