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ADF4113HV Datasheet, PDF (1/20 Pages) Analog Devices – High Voltage Charge Pump, PLL Synthesizer
FEATURES
High voltage charge pump (15 V)
2.7 V to 5.5 V power supply
200 MHz to 4.0 GHz frequency range
Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113
ADF4106, and ADF4002 synthesizers
Two selectable charge pump currents
Digital lock detect
Power-down mode
Loop filter design possible with ADIsimPLL™
APPLICATIONS
Applications using high voltage VCOs
IF/RF local oscillator (LO) generation in base stations
Point-to-point radio LO generation
Clock for analog-to-digital and digital-to-analog converters
Wireless LANs, PMR
Communications test equipment
High Voltage
Charge Pump, PLL Synthesizer
ADF4113HV
GENERAL DESCRIPTION
The ADF4113HV is an integer-N frequency synthesizer with a
high voltage charge pump (15 V). The synthesizer is designed
for use with voltage controlled oscillators (VCOs) that have
high tuning voltages (up to 15 V). Active loop filters are often
used to achieve high tuning voltages, but the ADF4113HV
charge pump can drive a high voltage VCO directly with a
passive-loop filter. The ADF4113HV can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. It consists of a
low noise digital phase frequency detector (PFD), a precision
high voltage charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1).
A simple 3-wire interface controls all of the on-chip registers.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
CPGND
REFERENCE
RSET
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT
INPUT REGISTER
22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
19
13
N = BP + A
PRESCALER
P/P + 1
13-BIT
B COUNTER
LOAD
LOAD
6-BIT
A COUNTER
6
PHASE
FREQUENCY
CHARGE
PUMP
CP
DETECTOR
LOCK
DETECT
CURRENT
SETTING
AVDD
SDOUT
MUX
HIGH Z
MUXOUT
M3 M2 M1
ADF4113HV
CE
AGND
DGND
Figure 1.
Rev. 0
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