ADF4108S Datasheet, PDF (1/21 Pages) Analog Devices – PLL Frequency Synthesizer

PLL Frequency Synthesizer
ADF4108S
1.0. SCOPE
This specification documents the detail requirements for space qualified product manufactured on Analog
Devices, Inc.'s QML certified line per MIL-PRF-38535 Level V except as modified herein.
The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM brochure is to be
considered a part of this specification. http://www.analog.com/aeroinfo
This data sheet specifically details the space grade version of this product. A more detailed operational description
and a complete data sheet for commercial product grades can be found at www.analog.com/ADF4108.
2.0. Part Number: The complete part number(s) of this specification follows:
Part Number
Description
ADF4108L703F
Radiation tested to 50Krads, 1 to 7 GHz PLL Frequency Synthesizer
3.0.
Case Outline
The case outline(s) are as designated in MIL-STD-1835 as follows:
Outline letter
X
Descriptive designator
CDFP4-F16
Terminals
Package style
16 lead Bottom Brazed Flat Pack
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Terminal
Symbol
Rset
CP
CPGND
AGND
RFinB
RFinA
AVdd
REFin
DGND
CE
CLK
DATA
LE
MUXOUT
DVdd
Vp
Pin Type
Analog Input
Analog Output
Ground
Ground
Analog Input
Analog Input
Power
Analog Input
Ground
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output
Power
Power
Package: F
Pin Description
Bias for charge pump. Connecting a resistor between this pin and CPGND set the maximum
charge pump current to: Icp max = 25.5 / Rset. The nominal output voltage is 0.66V
Charge Pump Output. When enabled, this pin provides ±Icp to the external loop filter, which
in turn drives the external VCO.
Charge Pump Ground. Connect to low impedance ground.
Analog Ground. Connect to low impedance ground.
Complementary Input to the RF Prescaler. This pin must be decoupled to ground plane with a
small bypass capacitor, typically 100pF.
Input to the RF Prescaler. This pin must be ac-coupled to external VCO.
Analog supply voltage. 3.2V to 3.6V. AVdd and DVdd should be tied together externally and
properly bypassed.
Reference Input. This is a CMOS input with a nominal threshold of Vdd/2 and a equivalent
input resistance of 100kΩ.
Digital Ground. Connect to low impedance ground.
Chip Enable. High impedance CMOS input. A logic low on this pin powers down the part and
puts the charge pump output into three-state mode.
Serial Clock input. High impedance CMOS input. Used to clock in serial data to registers.
Serial Data Input. High impedance CMOS input. Data loaded MSB first with the 2 LSBs being
the control bits.
Load Enable. High impedance CMOS input. When LE rises, shift register data is loaded into
one of four latches selected using the control bits.
Muxtiplexer Output. Allows either lock detect, or frequency divided RF or REF to accessed
externally.
Digital Supply Voltage. 3.2V to 3.6V. AVdd and DVdd should be tied together externally and
properly bypassed.
Charge Pump Power Supply. Must be greater than or equal to Vdd and less than 5.5V.
Figure 1 - Terminal connections.
ASD0016548
Rev.A
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