ADF4106 Datasheet, PDF (1/20 Pages) Analog Devices – PLL Frequency Synthesizer

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FEATURES
6.0 GHz Bandwidth
2.7 V to 3.3 V Power Supply
Separate Charge Pump Supply (V_P) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
Programmable Anti-Backlash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
APPLICATIONS
Broadband Wireless Access
Instrumentation
Wireless LANS
Base Stations For Wireless Radio
PLL Frequency Synthesizer
ADF4106
GENERAL DESCRIPTION
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (Phase Frequency Detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP + A).
In addition, the 14-bit reference counter (R Counter), allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthe-
sizer is used with an external loop filter and VCO (Voltage
Controlled Oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high-frequency
systems, simplifying system architecture and lowering cost.
AV_DD DV_DD
FUNCTIONAL BLOCK DIAGRAM
V_P CPGND
REFERENCE
R_SET
REF_IN
CLK
DATA
LE
RF_INA
RF_INB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER
22
FUNCTION
LATCH
AB COUNTER
FROM
LATCH
FUNCTION
19
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AV_DD
SD_OUT
MUX
HIGH Z
MUXOUT
M3 M2 M1
ADF4106
REV. 0
CE AGND DGND
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© Analog Devices, Inc., 2001