ADF41020 Datasheet, PDF (1/16 Pages) Analog Devices – The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters.

Data Sheet
18 GHz Microwave PLL Synthesizer
ADF41020
FEATURES
18 GHz maximum RF input frequency
Integrated SiGe prescaler
Software compatible with the ADF4106/ADF4107/ADF4108
family of PLLs
2.85 V to 3.15 V PLL power supply
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Microwave point-to-point/multipoint radios
Wireless infrastructure
VSAT radios
Test equipment
Instrumentation
GENERAL DESCRIPTION
The ADF41020 frequency synthesizer can be used to implement
local oscillators as high as 18 GHz in the up conversion and
down conversion sections of wireless receivers and transmitters.
It consists of a low noise, digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, and high frequency programmable feedback dividers
(A, B, and P). A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). The synthesizer
can be used to drive external microwave VCOs via an active
loop filter. Its very high bandwidth means a frequency doubler
stage can be eliminated, simplifying system architecture and
reducing cost. The ADF41020 is software-compatible with the
existing ADF4106/ADF4107/ADF4108 family of devices from
Analog Devices, Inc. Their pinouts match very closely with
the exception of the ADF41020’s single-ended RF input pin,
meaning only a minor layout change is required when updating
current designs.
REF_IN
AV_DD DV_DD
FUNCTIONAL BLOCK DIAGRAM
V_{P GND}
R COUNTER
PHASE
FREQUENCY
DETECTOR
REFERENCE
R_SET
CHARGE
PUMP
CP
CLK
DATA
LE
24-BIT INPUT
REGISTER
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
3pF
RF_IN
50Ω
N = 4(BP + A)
DIVIDE
BY 4
P/P+ 1
A AND B
COUNTERS
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AV_DD
SD_OUT
MUX
HIGH-Z
MUXOUT
M3 M2 M1
ADF41020
GND
CE
GND
Figure 1.
Rev. 0
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