ADF4007_15 Datasheet, PDF (1/16 Pages) Analog Devices – High Frequency Divider/PLL Synthesizer

Data Sheet
High Frequency Divider/PLL Synthesizer
ADF4007
FEATURES
7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (V_P) allows extended tuning
voltage in 3 V systems
R_SET control of charge pump current
Hardware power-down mode
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
GENERAL DESCRIPTION
The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency detector), a
precision charge pump, and a divider/prescaler. The divider/
prescaler value can be set by two external control pins to one of
four values (8, 16, 32, or 64). The reference divider is permanently
set to 2, allowing an external REF_IN frequency of up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO (voltage
controlled oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high frequency
systems, simplifying system architecture and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
V_DD
V_P CPGND R_SET
REF_IN
ADF4007
R COUNTER
÷2
REFERENCE
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
RF_INA
RF_INB
N COUNTER
÷ 8, ÷ 16,
÷ 32, ÷ 64
MUX
MUXOUT
N2
N1
GND
Figure 1.
M2 M1
Rev. B
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