ADF4001 Datasheet, PDF (1/16 Pages) Analog Devices – 200 MHz Clock Generator PLL

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200 MHz Clock Generator PLL
ADF4001
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V_P) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware-Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead Chip Scale Package
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable refer-
ence signals. It consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, and a programmable 13-bit N counter. In
addition, the 14-bit reference counter (R Counter) allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthesizer
is used with an external loop filter and VCO (Voltage Controlled
Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).
The N min value of 1 allows flexibility in clock generation.
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
FUNCTIONAL BLOCK DIAGRAM
AV_DD
DV_DD
V_P
CPGND
R_SET
REF_IN
CLK
DATA
LE
RF_INA
RF_INB
ADF4001
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT
INPUT REGISTER ₂₂
FUNCTION
LATCH
SD_OUT
N COUNTER
LATCH
13
13-BIT
N COUNTER
REFERENCE
PHASE
FREQUENCY
CHARGE
CP
DETECTOR
PUMP
LOCK DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AV_DD
SD_OUT
MUX
HIGH Z
MUXOUT
CE
AGND
DGND
M3 M2 M1
REV. 0
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© Analog Devices, Inc., 2001