ADCMP606 Datasheet, PDF (1/16 Pages) Analog Devices – Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators

Preliminary Technical Data
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
ADCMP606/ADCMP607
FEATURES
10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
CML-compatible output stage
1 ns propagation delay
50 mW at 2.5 V
Shutdown pin (ADCMP607 only)
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP606/ADCMP607 are very fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from VEE − 0.5 V to VCC + 0.5 V,
low noise CML-compatible output drivers, and TTL-/CMOS-
compatible latch inputs with adjustable hysteresis and/or
shutdown inputs.
The device offers 1 ns propagation delay with 2 ps RMS random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
FUNCTIONAL BLOCK DIAGRAM
V_CCI
V_CCO
(ADCMP607 Only)
V_P NONINVERTING
INPUT
V_N INVERTING
INPUT
ADCMP606/
ADCMP607
CML
Q OUTPUT
Q OUTPUT
LE/HYS INPUT (ADCMP607 Only)
S_DN INPUT (ADCMP607 Only)
Figure 1.
V_CCO 1
V_CCI 2
V_EE 3
PIN 1
INDICATOR
ADCMP607
TOP VIEW
(Not to Scale)
9 V_EE
8 LE/HYS
7 S_DN
Figure 2.LFCSP Pin Configuration
to +6 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to support
a wide input signal range with independent output level control
and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, high speed latch and programmable hysteresis
features are also provided with a unique single-pin control option.
The ADCMP606 is available in a 6-lead SC70 package, and the
ADCMP607 is available in a 12-lead LSCFP package.
Rev. PrA
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