ADCMP563_05 Datasheet, PDF (1/16 Pages) Analog Devices – Dual, High Speed ECL Comparators

Dual, High Speed ECL Comparators
ADCMP563/ADCMP564
FEATURES
Differential ECL-compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
GENERAL DESCRIPTION
The ADCMP563/ADCMP564 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of high speed comparators.
A separate programmable hysteresis pin is available on the
ADCMP564.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals
FUNCTIONAL BLOCK DIAGRAM
HYS*
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP563/
ADCMP564
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
*ADCMP564 ONLY
Figure 1.
QA 1
16 QB
QA 2
15 QB
GND 3
LEA 4
LEA 5
V_EE 6
–INA 7
ADCMP563
BRQ
TOP VIEW
(Not to Scale)
14 GND
13 LEB
12 LEB
11 V_CC
10 –INB
+INA 8
9 +INB
GND 1
20 GND
QA 2
19 QB
QA 3
GND 4
LEA 5
LEA 6
18 QB
ADCMP564 _{17 GND}
BRQ
TOP VIEW ^{16 LEB}
(Not to Scale) _{15 LEB}
V_EE 7
–INA 8
14 V_CC
13 –INB
+INA 9
12 +INB
HYSA 10
11 HYSB
Figure 2. ADCMP563 16-Lead QSOP Figure 3. ADCMP564 20-Lead QSOP
GND 1
QA QA QB
16 15 14
PIN1
QB
13
12 GND
LEA 2
LEA 3
V_EE 4
ADCMP563
BCP
TOP VIEW
(Not to Scale)
11 LEB
10 LEB
9 V_CC
567
8
–INA +INA +INB –INB
Figure 4. ADCMP563 16-Lead LFCSP
that are fully compatible with ECL 10 K and 10 KH logic
families. The outputs provide sufficient drive current to directly
drive transmission lines terminated in 50 Ω to −2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
The ADCMP563/ADCMP564 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. B
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infringements of patents or other rights of third parties that may result from its use.
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