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ADCLK950 Datasheet, PDF (1/12 Pages) Analog Devices – Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer
Two Selectable Inputs, 10 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK950
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK950 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon german-
ium (SiGe) bipolar process. This device is designed for high
speed applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK950 features 10 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC − 2 V for a total differential
output swing of 1.6 V.
The ADCLK950 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ADCLK950
LVPECL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
VREF0
REFERENCE
Q3
VT0
Q4
Q4
CLK0
CLK0
Q5
VT1
Q5
CLK1
Q6
CLK1
Q6
Q7
IN_SEL
Q7
VREF1
REFERENCE
Q8
Q8
Q9
Q9
Figure 1.
Rev. 0
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