ADCLK905 Datasheet, PDF (1/16 Pages) Analog Devices – Ultrafast SiGe ECL Clock/Data Buffers

Ultrafast SiGe
ECL Clock/Data Buffers
ADCLK905/ADCLK907/ADCLK925
FEATURES
95 ps propagation delay
7.5 GHz toggle rate
60 ps typical output rise/fall
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: −40°C to +125°C
2.5 V to 3.3 V power supply (VCC − VEE)
APPLICATIONS
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
Threshold detection
Converter clocking
GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
VEE to the negative supply.
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total
differential output swing of 1.6 V.
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
TYPICAL APPLICATION CIRCUITS
V_REF
V_T
D
D
V_CC
Q
Q
V_EE
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
V_REF1
V_T1
D1
D1
V_CC
Q1
Q1
V_EE
V_EE
D2
Q2
D2
Q2
V_CC
V_T2
V_REF2
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
V_REF
V_CC
V_T
Q1
Q1
D
D
Q2
Q2
V_EE
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
Rev. 0
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