ADC1121 Datasheet, PDF (1/6 Pages) Analog Devices – Low Power Analog to Digital Converter

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- ~ ANALOG
W DEVICES
LowPower
Analogto DigitaCl onverter
ADC1121
FEATURES
12 Bit Resolution and Accuracy
CMOS Compatible
Very Low Power Consumption
Exceptional Power Supply Rejection
Can Operate From Single Battery
No Missing Codes, 0 to +70°C
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OB _{GENERAL DESCRIPTION}
S _{The CMOS compatible ADC112I requires less than 6 micro-}
O ^{joules of energy to perform a complete, 12 bit analog-to-digital}
conversion. In addition, it has :to.OI% relative accuracy, a 70fJ.s
8 L maximum conversion time, a maximum power consumption of
IOOmWfor continuous conversions, and no missing codes from
E _{0 to +70°C. Power may be supplied by a single +I2Y to +ISY}
--^'--^' ,nnn^{T source, but the logic portions of the converter may also be}
powered by a separate +SY to +ISY supply to permit logic
nnr m_E- _{level matching. If batteries are used as a power source, the}
the LSB decision, the clock returns to logic' l' and the STATUS
output returns to logic '0'.
The serial data output is of the non-return-to-zero (NRZ) type.
The data is available, MSB first, at the third and subsequent
positive~oing dock transitions,
CONVERT
COMMAND.-I
GATED
CLOCK
L
1_L...-....
U UU UUU
resulting voltage droop will have little effect on the ADC112I
accuracy due to its excellent power supply rejection.
.--J STATUS
~
The ADC112I accepts analog inputs in the range of 0 to +SY,
MSB_{--_J}^'_L: _IL-
....
0 to +IOY, :tSY, or :tIOY and produces both parallel and serial
digital outputs. Parallel outputs are binary, offset binary, or
BIT2=~""
two's complement coded; serial outputs are binary or offset
binary coded.
B.3I-T-- ~
....
The special combination of high performance and low power
exhibited by this 2" x 4" x 0.4" (SIx 102 x IOmm) module
makes it ideal for use in applications such as remote and port-
able instrumentation, and large data handling networks-
TIMING
When the convert command is set to logic" 1", the internal
clock starts to run. The first '1' to '0' clock transition sets the
STATUS output to logic '1' and sets the MSB through LSB and
SERIAL output lines to logic '0'. The CONYERT COMMAND
input may be returned to logic '0' lOOns after this clock tran-
sition but may also remain at logic '1' until SOOnsbefore the
sixth clock transition. The MSB decision process starts on the
second negative~oing clock edge and concludes one clock
period later. The bit decisions continue at the rate of one per
clock cycle until the LSB decision has finally been made. After
8
:LSB
SERIAL
OUTPUT
1:
in n
L.J L-.J L
Ms! t L 3
10) BIT 2 10)
11)
.... ~
---1
I
--_of
LSB
101
Figure 1. Timing Diagram
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for itS use; nor for any infringementS of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
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