ADC1100_15 Datasheet, PDF (1/4 Pages) Analog Devices – LOW COST DUAL SLOPE A/D CONVERTER

~ ANALOG
W DEVICES
LowCost
DualSlopeAID Converter
FEATURES
3% BCD Digits or 11 Bits Plus Sign
Accepts Bipolar or Unipolar Input Signals
Requires Only +5V Power
4OdB Normal Mode Noise Rejection
Analog Input Overvoltage Protected
Automatic Zero Correction
Can Drive Display and/or Feed Computer
User Choice of Three Triggering Methods
OBSOLETE ^{Capableof Ratiometric Operation}
GENERAL DESCRIPTION
The ADC1100 is a dual slope integrating analog-to-digital con-
verter with 3Y2BCD digit or 11 binary bit resolution. It accepts
an analog input signal within the nominal range of :t200mV,
and converts the average value during the input integration
time period to parallel output sign-magnitude BCD or sign-
magnitude binary data. The unit is packaged in a small 2" x
4" x 0.4" module, and requires only +5V power.
EXCELLENT NOISE REJECTION
TIMING INFORMATION
As shown in Figure 1, each conversion begins with an auto-
matic zero correction cycle. Polarity data is valid anytime
after the completion of the input signal integration time
period, and it remains latched in one polarity until such time
as a conversion is performed with an input signal of the
opposite polarity. The digital output data is valid no later
than SOns prior to the READY output's "0" to "I" transi-
tion. This "set up" time is sufficient to allow the output data
Because the ADCIIOO's output is based on the average value
to be strobed into a following register or latch on the READY
of the input signal during the input integration time period, in- ^{output's "0" to "1" edge. In the event of an overrange input}
accuracies due to noise spikes are greatly suppressed. In addi-
signal, the OVERLOAD output will go from "0" to "1" at the
end of the conversion. It will remain latched in the "1" state
tion, with the input integration time period set equal to one
cycle of the power line, the integral of any power line noise is ^{until a normal conversion has been performed.}
equal to zero. This results in a normal mode power line noise
rejection ratio of at least 40dB. By locking the input integra-
tion time precisely to one period of the power line using an
external phase locked loop, this ratio can be increased to over
BOdB. Since the excellent noise rejection is achieved without
any input filtering, the analog input settling time required
prior to the commencement of a conversion is zero.
APPLICATIONS
With the only power required being +5V, and with its excellent
TRIGGER
INTEGRATOR
1
READY
~~~
OVERLOAD
f
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ZERO
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16 67ms
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noise rejection, the ADC1100 is an ideal choice for installation
at transducer locations. The BCD coded version is also well
'Reference ;ntegration tome t? 20~~V x 16.67ms. In the event of an over
loaded ;nput. tm" " Sams. IThe tim., shown are thme obt"ned when the
un;!;s set for 60Hz noise re,ection.1
suited for many behind-the-panel applications because it allows
the instrument designer complete freedom in choosing a dis-
play. For example, it may be desirable to share a single display
with more than one digital output device, or to display a digital
output scaled quite differently from the ADCllOO/BCD's
Figure 1. Timing Diagram
:tI99.9mV input range.
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AID CONVERTERS 431
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