ADAS1000 Datasheet, PDF (1/3 Pages) Analog Devices – Low Power, 5-Electrode Electrocardiogram (ECG) Analog Front End

Low Power, 5-Electrode
Electrocardiogram (ECG) Analog Front End
Preliminary Technical Data
ADAS1000
FEATURES
Biopotential signals in; digitized signals out
5 acquisition (ECG) channels + 1 driven lead
Parallel ICs for up to 10+ Electrode measurements
AC and DC Leads Off Detection
Internal Pace Detection Algorithm on 3 leads
Support for users own pace
Thoracic Impedance Measurement (internal/external path)
Selectable Reference Lead
Scalable Noise vs. Power Control
Low Power Operation from:
11mW (one lead), 14mW (3 leads), 19mW (all electrodes)
Power Down Modes
Lead or Electrode Data available
Supports AAMI EC11:1991/(R)2001/(R)2007,
EC13:2002/(R)2007, IEC60601-1 ed. 3.0b, 2005, IEC60601-
2-25 ed. 1.0b, IEC60601-2-27 ed. 2.0, 2005 IEC60601-2-51
ed. 1.0, 2005
Fast Overload Recovery
Low or High speed Data Output Rates
Serial interface SPI®-/QSPI™-/DSP-compatible
56 lead LFCSP package (8mm x8mm)
64 lead LQFP package (10mm x10mm Body size)
APPLICATIONS
ECG: Monitor & Diagnostic
Bedside Patient Monitoring, Portable Telemetry, Holter,
AED, Cardiac Defibrillators, Ambulatory Monitors, Pace
Maker Programmer, Patient Transport, Stress testing,
GENERAL DESCRIPTION
The ADAS1000 measures electro cardiac (ECG) signals,
thoracic impedance, pacing artifacts, lead on/off status and
outputs this information in the form of a data frame supplying
either Lead/Vector or Electrode data at programmable data
rates. Its low power and small size make it suitable for portable,
battery powered applications. The high performance also makes
it suitable for higher end diagnostic machines.
The ADAS1000 is designed to simplify the task of acquiring and
ensuring quality ECG signals. Value-added cardiac post-
processing is executed externally on a DSP, microprocessor or
FPGA. Several digital output options ensure flexibility when
monitoring and analyzing signals. The ADAS1000 provides a
low power, small data acquisition system for biopotential
applications.
REFIN REFOUT
Voltage
Reference
CALIBRATION
DAC
RESPIRATION
DAC
CAL_DAC
_IO _{CM_IO}
FUNCTIONAL BLOCK DIAGRAM
SHIELD
DRIVE
SHIELD
DRIVE
AMP
VCM
(1.5V)
RLD_SJ
RLD_FB RLD_OUT
DRIVEN
LEAD
AMP
AC LEADS
OFF DAC
MUXES
ELECTRODES
x5
OPTIONAL
SHIELD
DRIVE
EXT RESP 1
EXT RESP 2
EXT RESP 3
COMMON
MODE AMP
5 x ECG PATH
AMP
ADC
AMP
ADC
RESPIRATION PATH
LEADS
OFF
DETECTION
PACE
DETECTION
FILTERS,
CONTROL
&
INTERFACE
LOGIC
CLOCK GEN/OSC
/EXTERNAL CLK
SOURCE
XTAL
IN
XTAL
OUT
CS
SCLK
SDI
SDO
DRDY
STANDARD
SERIAL INTERFACE
GPIO0/MCS
GPIO1/MSCLK
GPIO2/MSDO
GPIO3
CLK_IO
SECONDARY
MASTER INTERFACE
FOR PACE
Figure 1 Functional Block Diagram
8.192MHz
Cyrstal or Clock
Rev. Pr.D
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