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AD9994 Datasheet, PDF (1/2 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator
FEATURES
10-phase or 12-phase vertical transfer clocking
Supports 4-field and 5-field CCD readout
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit 36 MHz A/D converter
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with < 600 ps resolution
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
64-lead LFCSP package (9 mm × 9 mm, 0.5 mm pitch)
APPLICATION
Digital still cameras
12-Bit CCD Signal Processor with
Precision Timing TM Generator
AD9994
GENERAL DESCRIPTION
The AD9994 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with A/D conversion, combined with a full-function
programmable timing generator. The timing generator is capable
of up to 12-phase vertical clocking to support advanced CCDs
with 4-field and 5-field readout. A Precision Timing core allows
adjustment of high speed clocks with approximately 600 ps
resolution at 36 MHz operation.
The AD9994 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 12-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a 64-lead LFCSP, the AD9994 is specified over an
operating temperature range of –25°C to +85°C.
For more information about the AD9994, email Analog Devices
at afe.ccd@analog.com.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
CDS
6dB TO 42dB
VGA
VREF
12-BIT
ADC
–3dB, 0dB, +3dB, +6dB
CLAMP
INTERNAL CLOCKS
RG
HL
4
HORIZONTAL
DRIVERS
PRECISION
TIMING
GENERATOR
H1 TO H4
V1 TO V10
(V1 TO V12)
VSG1 TO VSG8
(VSG1 TO VSG6)
10 OR 12
8 OR 6
VERTICAL
TIMING
CONTROL
SYNC
GENERATOR
AD9994
12
DOUT
DCLK
MSHUT
STROBE
INTERNAL
REGISTERS
VSUB VSUB
HD VD SYNC CLI CLO SL SCK DATA
Figure 1.
Rev. Sp0
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