AD9888 Datasheet, PDF (1/32 Pages) Analog Devices – 100/140/170/205 MSPS Analog Flat Panel Interface

a
FEATURES
205 MSPS Maximum Conversion Rate
500 MHz Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for “Hot Plugging”
2:1 Analog Input Mux
4:2:2 Output Format Mode
Midscale Clamping
Power-Down Mode
Low Power: <1 W Typical @ 205 MSPS
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
100/140/170/205 MSPS Analog
Flat Panel Interface
AD9888
FUNCTIONAL BLOCK DIAGRAM
R_IN
R_IN
G_IN
G_IN
B_IN
B_IN
HSYNC
HSYNC
VSYNC
VSYNC
SOGIN
SOGIN
COAST
CLAMP
CKINV
CKEXT
FILT
2:1
MUX
CLAMP
2:1
MUX
CLAMP
2:1
MUX
CLAMP
8
8
A/D
8
8
8
A/D
8
8
8
A/D
8
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2
REF
R_OUTA
R_OUTB
G_OUTA
G_OUTB
B_OUTA
B_OUTB
DATACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
AD9888
SCL
SDA
A0
SERIAL REGISTER
AND
POWER MANAGEMENT
GENERAL DESCRIPTION
The AD9888 is a complete 8-bit, 205 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 205 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports resolutions up to UXGA (1600 × 1200 at 75 Hz).
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface with a 205 MHz triple ADC with
internal 1.25 V reference, PLL to generate a pixel clock from
HSYNC and COAST, midscale clamping, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and HSYNC and COAST signals.
Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9888’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output frequencies range from
10 MHz to 205 MHz. PLL clock jitter is less than 450 ps p-p
typical at 205 MSPS. When the COAST signal is presented, the
PLL maintains its output frequency in the absence of HSYNC.
A sampling phase adjustment is provided. Data, HSYNC, and
Clock output phase relationships are maintained. The PLL can
be disabled and an external clock input provided as the pixel
clock. The AD9888 also offers full sync processing for compos-
ite sync and Sync-on-Green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9888 is pro-
vided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over the 0°C to 70°C temperature range.
REV. A
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use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 2002