AD9880 Datasheet, PDF (1/64 Pages) Analog Devices – Analog/HDMI Dual Display Interface

FEATURES
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead LQFP Pb-free package
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI v 1.1, DVI v 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
(HDCP 1.1)
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TV
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9880 offers designers the flexibility of an analog interface
and high definition multimedia interface (HDMI) receiver inte-
grated on a single chip. Also included is support for high band-
width digital content protection (HDCP).
Analog Interface
The AD9880 is a complete 8-bit 150 MSPS monolithic analog inter-
face optimized for capturing component video (YPbPr) and RGB
graphics signals. Its 150 MSPS encode rate capability and full power
analog bandwidth of 330 MHz supports all HDTV formats (up to
1080 p) and FPD resolutions up to SXGA (1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with internal
1.25 V reference, a phase-locked loop (PLL), and programmable
gain, offset, and clamp control. The user provides only 1.8 V and
3.3 V power supplies, analog input, and Hsync. Three-state
Rev. 0
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Analog/HDMI
Dual Display Interface
AD9880
FUNCTIONAL BLOCK DIAGRAM
R/G/B OR YPbPr_IN0
R/G/B OR YPbPr_IN1
ANALOG INTERFACE
2:1
MUX
CLAMP
R/G/B 8X3
A/D
or YCbCr
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
SCL
SDA
RX0+
RX0–
RX1+
RX1–
RX2+
RX2–
RXC+
RXC–
R_TERM
MCL
MDA
DDCSCL
DDCSDA
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2 _DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
HDMI RECEIVER
R/G/B 8X3
OR YCbCr
2 DATACK
DE
H_SYNC
V_SYNC
4
HDCP
R/G/B 8X3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
SOGOUT
DE
SPDIF OUT
8-CHANNEL
I₂S OUT
SCLK
MCLK
LRCLK
AD9880
Figure 1.
CMOS outputs can be powered from 1.8 V to 3.3 V. The
AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
Digital Interface
The AD9880 contains a HDMI 1.1-compatible receiver and sup-
ports all HDTV formats (up to 1080 p and 720 p) and display
resolutions up to SXGA (1280 × 1024 @75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive encrypted
video content. The AD9880 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renewa-
bility of the authentication during transmission, as specified by the
HDCP v 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9880 is provided
in a space-saving, 100-lead LQFP surface-mount Pb-free plastic
package and is specified over the 0°C to 70°C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.