AD9866 Datasheet, PDF (1/48 Pages) Analog Devices – Broadband Modem Mixed Signal Front End

Broadband Modem Mixed-Signal Front End
AD9866
FEATURES
Low cost 3.3 V CMOS MxFE^TM for broadband modems
12-bit D/A converter
2×/4× interpolation filter
200 MSPS DAC update rate
Integrated 23 dBm line driver with 19.5 dB gain control
12-bit, 80 MSPS A/D converter
−12 dB to +48 dB low noise RxPGA (< 2.5 nV/rtHz)
Third order, programmable low-pass filter
Flexible digital data path interface
Half- and full-duplex operation
Backward-compatible with AD9975 and AD9876
Various power-down/reduction modes
Internal clock multiplier (PLL)
2 auxiliary programmable clock outputs
Available in 64-lead chip scale package or bare die
APPLICATIONS
Powerline networking
VDSL and HPNA
GENERAL DESCRIPTION
The AD9866 is a mixed-signal front end (MxFE) IC for
transceiver applications requiring Tx and Rx path functionality
with data rates up to 80 MSPS. Its flexible digital interface, power
saving modes, and high Tx-to-Rx isolation make it well-suited
for half- and full-duplex applications. The digital interface is
extremely flexible allowing simple interfaces to digital back
ends that support half- or full-duplex data transfers, thus often
allowing the AD9866 to replace discrete ADC and DAC
solutions. Power saving modes include the ability to reduce
power consumption of individual functional blocks or to power
down unused blocks in half-duplex applications. A serial port
interface (SPI®) allows software programming of the various
functional blocks. An on-chip PLL clock multiplier and
synthesizer provide all the required internal clocks, as well as
two external clocks from a single crystal or clock source.
The Tx signal path consists of a bypassable 2×/4× low-pass
interpolation filter, a 12-bit TxDAC, and a line driver. The
transmit path signal bandwidth can be as high as 34 MHz at an
input data rate of 80 MSPS. The TxDAC provides differential
current outputs that can be steered directly to an external load
FUNCTIONAL BLOCK DIAGRAM
PWR DWN
MODE
TXEN/SYNC
TXCLK
ADIO[11:6]/
Tx[5:0]
ADIO[5:0]/
Rx[5:0]
RXE/SYNC
RXCLK
AGC[5:0]
SPI
AD9866
12
2-4X
TxDAC
IAMP
0 TO –7.5dB
0 TO –12dB
CLK
SYN.
2^M CLK
MULTIPLIER
12
ADC
80MSPS
2-POLE
LPF
1-POLE
LPF
6
4
REGISTER
CONTROL
0 TO 6dB – 6 TO 18dB –6 TO 24dB
∆ = 1dB ∆ = 6dB
∆ = 6dB
IOUT_G+
IOUT_N+
IOUT_N–
IOUT_G–
CLKOUT_1
CLKOUT_2
OSCIN
XTAL
RX+
RX–
Figure 1.
or to an internal low distortion current amplifier. The current
amplifier (IAMP) can be configured as a current- or voltage-
mode line driver (with two external npn transistors) capable of
delivering in excess of 23 dBm peak signal power. Tx power can
be digitally controlled over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier
(RxPGA), a tunable low pass filter (LPF), and a 12-bit ADC.
The low noise RxPGA has a programmable gain range of
−12 dB to +48 dB in 1 dB steps. Its input referred noise is less
than 3.3 nV/rtHz for gain settings beyond 30 dB. The receive
path LPF cutoff frequency can be set over a 15 MHz to 35 MHz
range or simply bypassed. The 12-bit ADC achieves excellent
dynamic performance over a 5 MSPS to 80 MSPS span. Both
the RxPGA and the ADC offer scalable power consumption
allowing power/performance optimization.
The AD9866 provides a highly integrated solution for many
broadband modems. It is available in a space saving, 64-lead
lead frame chip scale package (LFCSP), and is specified over the
commercial (−40°C to +85°C) temperature range.
Rev. A
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