AD9854ASVZ Datasheet, PDF (1/52 Pages) Analog Devices – CMOS 300 MSPS Quadrature Complete DDS

CMOS 300 MSPS Quadrature
Complete DDS
AD9854
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CLOCK IN
DIFF/SINGLE
SELECT
FSK/BPSK/HOLD
DATA IN
REF
CLK
BUFFER
SYSTEM CLOCK
4× TO 20×
REF CLK
MULTIPLIER
48 48
MUX
SYSTEM
CLOCK
48
3
MUX
DELTA
FREQUENCY
RATE TIMER
MUX
DDS CORE
17
17
14
MUX
12
I
12
Q
INV ^{DIGITAL MULTIPLIERS}
SINC
12
FILTER
12-BIT
I
DAC
INV
SINC
FILTER
SYSTEM
CLOCK
12
12-BIT
Q DAC OR
CONTROL
DAC
SYSTEM
CLOCK
12 12
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
ANALOG
OUT
DAC R_SET
ANALOG
OUT
ANALOG
IN
2
48 SYSTEM 48
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
48
14
14
12 12
FREQUENCY FIRST 14-BIT SECOND 14-BIT I AND Q 12-BIT 12-BIT DC
TUNING PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL
WORD 2
WORD
WORD
COMPARATOR
CLOCK
OUT
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CLOCK
INT
CK
Q
D
EXT
PROGRAMMING REGISTERS
SYSTEM
÷2
CLOCK
AD9854
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
BUS
I/O PORT BUFFERS
OSK
GND
+V_S
READ
WRITE SERIAL/
PARALLEL
SELECT
Figure 1.
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
Rev. E
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