AD9853_15 Datasheet, PDF (1/31 Pages) Analog Devices – Programmable Digital QPSK/16-QAM Modulator

a
Programmable Digital
QPSK/16-QAM Modulator
AD9853
FEATURES
GENERAL DESCRIPTION
Universal Low Cost Solution for HFC Network
The AD9853 integrates a high speed direct-digital synthesizer
Return-Channel T_X Function: 5 MHz–42 MHz/
(DDS), a high performance, high speed digital-to-analog con-
5 MHz–65 MHz
verter (DAC), digital filters and other DSP functions onto a
165 MHz Internal Reference Clock Capability
single chip, to form a complete and flexible digital modulator
Includes Programmable Pulse-Shaping FIR Filters and
device. The AD9853 is intended to function as a modulator in
Programmable Interpolating Filters
network applications such as interactive HFC, WLAN and
FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation
MMDS, where cost, size, power dissipation, functional integra-
Formats
tion and dynamic performance are critical attributes.
6؋ Internal Reference Clock Multiplier
The AD9853 is fabricated on an advanced CMOS process and
Integrated Reed-Solomon FEC Function
it sets a new standard for CMOS digital modulator performance.
Programmable Randomizer/Preamble Function
The device is loaded with programmable functionality and
OBSOLETE Supports Interoperable Cable Modem Standards
Internal SINx/x Compensation
>50 dB SFDR @ 42 MHz Output Frequency (Single Tone)
Controlled Burst Mode Operation
+3.3 V to +5 V Single Supply Operation
Low Power: 750 mW @ Full Clock Speed (3.3 V Supply)
Space Saving Surface Mount Packaging
APPLICATIONS
HFC Data, Telephony and Video Modems
Wireless LAN
provides a direct interface port to the AD8320, digitally-
programmable cable driver amplifier. The AD9853/AD8320
chipset forms a highly integrated, low power, small footprint
and cost-effective solution for the HFC return-path requirement
and other more general purpose modulator applications.
The AD9853 is available in a space saving surface mount pack-
age and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
DATA IN
R-S
FEC
DATA
XOR DELAY
& MUX
ENCODER:
FSK
QPSK
DQPSK
16-QAM
D16-QAM
FIR
FILTER
INTERPOLATION
FILTER
FIR
INTERPOLATION
AD9853
10
INV
SYNC
FILTER
10-BIT
10 ^DAC
A_OUT
TO LP FILTER
AND AD8320
RANDOMIZER
PREAMBLE
INSERTION
FILTER
FILTER
GAIN
CONTROL TO
CABLE DRIVER
AMPLIFER
SINE
COSINE
DRIVER AMP
DDS
CLOCK
6؋
CONTROL FUNCTIONS
REF CLOCK IN
FEC T_XENABLE RESET
ENABLE/
DISABLE
SERIAL CONTROL BUS:
32-BIT OUTPUT FREQUENCY TUNING WORD
INPUT DATA RATE/MODULATION FORMAT
FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION
FIR FILTER COEFFICIENTS
REF CLOCK MULTIPLIER ENABLE
I/Q PHASE INVERT
SLEEP MODE
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 1999