AD9853 Datasheet, PDF (1/31 Pages) Analog Devices – Programmable Digital OPSK/16-QAM Modulator

a
Programmable Digital
QPSK/16-QAM Modulator
AD9853
FEATURES
Universal Low Cost Solution for HFC Network
Return-Channel T_X Function: 5 MHz–42 MHz/
5 MHz–65 MHz
165 MHz Internal Reference Clock Capability
Includes Programmable Pulse-Shaping FIR Filters and
Programmable Interpolating Filters
FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation
Formats
6؋ Internal Reference Clock Multiplier
Integrated Reed-Solomon FEC Function
Programmable Randomizer/Preamble Function
Supports Interoperable Cable Modem Standards
Internal SINx/x Compensation
>50 dB SFDR @ 42 MHz Output Frequency (Single Tone)
Controlled Burst Mode Operation
+3.3 V to +5 V Single Supply Operation
Low Power: 750 mW @ Full Clock Speed (3.3 V Supply)
Space Saving Surface Mount Packaging
APPLICATIONS
HFC Data, Telephony and Video Modems
Wireless LAN
GENERAL DESCRIPTION
The AD9853 integrates a high speed direct-digital synthesizer
(DDS), a high performance, high speed digital-to-analog con-
verter (DAC), digital filters and other DSP functions onto a
single chip, to form a complete and flexible digital modulator
device. The AD9853 is intended to function as a modulator in
network applications such as interactive HFC, WLAN and
MMDS, where cost, size, power dissipation, functional integra-
tion and dynamic performance are critical attributes.
The AD9853 is fabricated on an advanced CMOS process and
it sets a new standard for CMOS digital modulator performance.
The device is loaded with programmable functionality and
provides a direct interface port to the AD8320, digitally-
programmable cable driver amplifier. The AD9853/AD8320
chipset forms a highly integrated, low power, small footprint
and cost-effective solution for the HFC return-path requirement
and other more general purpose modulator applications.
The AD9853 is available in a space saving surface mount pack-
age and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
DATA IN
R-S
FEC
DATA
XOR DELAY
& MUX
RANDOMIZER
PREAMBLE
INSERTION
ENCODER:
FSK
QPSK
DQPSK
16-QAM
D16-QAM
CLOCK
6؋
FIR
FILTER
FIR
FILTER
INTERPOLATION
FILTER
AD9853
10
INV
SYNC
FILTER
10-BIT
10 ^DAC
INTERPOLATION
FILTER
SINE
COSINE
DDS
CONTROL FUNCTIONS
A_OUT
GAIN
CONTROL TO
DRIVER AMP
TO LP FILTER
AND AD8320
CABLE DRIVER
AMPLIFER
REF CLOCK IN
FEC T_XENABLE RESET
ENABLE/
DISABLE
SERIAL CONTROL BUS:
32-BIT OUTPUT FREQUENCY TUNING WORD
INPUT DATA RATE/MODULATION FORMAT
FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION
FIR FILTER COEFFICIENTS
REF CLOCK MULTIPLIER ENABLE
I/Q PHASE INVERT
SLEEP MODE
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 1999