AD9852_07 Datasheet, PDF (1/52 Pages) Analog Devices – CMOS 300 MSPS Complete DDS

FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and on/off
output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency hold function
CMOS 300 MSPS Complete DDS
AD9852
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CLOCK IN
DIFF/SINGLE
SELECT
FSK/BPSK/HOLD
DATA IN
REFCLK
BUFFER
SYSTEM CLOCK
4× TO 20×
REFCLK
MULTIPLIER
48 48
SYSTEM
CLOCK
MUX
3
MUX
DELTA
FREQUENCY
RATE TIMER
48
MUX
DDS CORE
17
17
14
MUX
12
I
Q
INV
SINC
FILTER
DIGITAL MULTIPLIERS
12
12-BIT
COSINE
DAC
SYSTEM
CLOCK
12-BIT
CONTROL
DAC
12
SYSTEM
CLOCK
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
ANALOG
OUT
DAC R_SET
ANALOG
OUT
ANALOG
IN
2
48 SYSTEM
48
48
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY FREQUENCY
TUNING
TUNING
WORD 1
WORD 2
14
FIRST 14-BIT
PHASE/OFFSET
WORD
14
12
SECOND 14-BIT
AM
12-BIT DC
PHASE/OFFSET MODULATION CONTROL
WORD
COMPARATOR
CLOCK
OUT
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CLOCK
INT
CLK
DQ
EXT
PROGRAMMING REGISTERS
SYSTEM
÷2
CLOCK
AD9852
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
BUS
I/O PORT BUFFERS
OSK
GND
+V_S
READ
WRITE SERIAL/
PARALLEL
SELECT
Figure 1.
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
Rev. E
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