AD9786_15 Datasheet, PDF (1/56 Pages) Analog Devices – 16-Bit, 200 MSPS/500 MSPS TxDAC

16-Bit, 200 MSPS/500 MSPS TxDAC+^® with
2×/4×/8× Interpolation and Signal Processing
AD9786
FEATURES
PRODUCT HIGHLIGHTS
16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
1. 16-bit, high speed, interpolating TxDAC+.
Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz
2. 2×/4×/8× user-selectable interpolating filter. The filter
WCDMA ACLR = 80 dBc @ 40 MHz IF
eases data rate and output signal reconstruction filter
DNL = ±0.3 LSB
requirements.
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters
3. 200 MSPS input data rate.
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single- or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
4. Ultra high speed, 500 MSPS DAC conversion rate.
5. Flexible clock with single-ended or differential input.
CMOS, 1 V p-p sine wave, and LVPECL capability.
Direct IF transmission features
Serial control interface
Versatile clock and data interface
3.3 V-compatible digital interface
On-chip 1.2 V reference
80-lead, thermally enhanced, TQFP_EP package
6. Complete CMOS DAC function. It operates from a 3.1 V
to 3.5 V single analog (AVDD) supply, 2.5 V digital supply,
and a 3.3 V digital (DRVDD) supply. The DAC full-scale
current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.
7. On-chip voltage reference. The AD9786 includes a
APPLICATIONS
1.20 V temperature-compensated band gap voltage
Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA,
IS136, TETRA
Instrumentation
RF signal generators, arbitrary waveform generators
HDTV transmitters
Broadband wireless systems
reference.
8. Multichip synchronization. Multiple AD9786 DACs can
be synchronized to a single master AD9786 to ease timing
design requirements and optimize image reject transmit
performance.
Digital radio links
Satellite systems
FUNCTIONAL BLOCK DIAGRAM
P1B[15:0]
P2B[15:0]
DATACLK
LATCH
2×
×1
LATCH
2×
2×
2×
I
0
90
f_DAC/2
f_DAC/4
f_DAC/8
0
90
0
90
Q
2×
2×
Δt
ZERO
STUFF
16-BIT DAC
HILBERT
FSADJ
REFIO
IOUTA
IOUTB
SDIO
SDO
CSB
SCLK
RESET
CLK+
CLK–
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. B
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