AD9773 Datasheet, PDF (1/19 Pages) Analog Devices – 12-Bit, 160 MSPS 2×/4×/8× Interpolating Dual TxDAC+ D/A Converter

PRELIMINARY TECHNICAL DATA
a
12-Bit, 160 MSPS
2×/4×/8× Interpolating
Dual TxDAC+^® D/A Converter
Preliminary Technical Data 01-19-01
AD9773
FEATURES
12 bit Resolution, 160 MSPS Conversion Rate
Selectable 2×/4×/8× Interpolating Filter
Programmable Channel Gain and Offset Adjustment
Fs/2,4,8 Digital Quadrature Modulation Capability
Direct IF Transmission Mode for 70MHz+ IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Excellent AC Performance
- SFDR -69dBc @ 2-35MHz
-WCDMA ACPR -70dB @ IF=16.25 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input
-Differential/Single Ended
-Sine Wave or TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface
-2’s Complement/Straight Binary Data Coding
-Dual Port or Single Port Interleaved Data
Single +3.3V Supply Operation
Power Dissipation: <700 mW @ 3.3V
On-chip 1.2 V Reference, 80-Lead LQFP
APPLICATIONS
Communications:
Analog Quadrature Modulation Architectures
3G, Multi-Carrier GSM, TDMA, CDMA Systems
Multi-Level QAM Modulators, Instrumentation
PRODUCT DESCRIPTION
The AD9773 is the 12 bit member of the AD977x family of
pin-compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+s. The AD977x family features a serial
port interface (SPI) providing a high level of programmabil-
ity thus allowing for enhanced system level options. These
options include: selectable 2×/4×/8× interpolation filters;
Fs/2, Fs/4 or Fs/8 digital quadrature modulation with image
rejection; a direct IF mode; programmable channel gain
and offset control; programmable internal clock divider;
straight binary or two’s complement data interface; and a
single port or dual port data interface.
PROGRAMABLE DUAL INTERPOLATION DAC
WITH IMAGE REJECTION/DIGITAL MODULATION
HALF-BAND HALF-BAND HALF-BAND
FILTER #1* FILTER #2* FILTER#3*
DATA
A S S E MB LE R
12
I 12
22
LATCH
22
22
COS
+
- /+
SIN
F_DAC/2,4,8
Q ¹²
12
LATCH
WRITE
SELECT
MUX
CONTROL
Ϭ2
CLOCK OUT
Ϭ2
22
22
Ϭ2
22
FILTE R
BYPASS MUX
SIN
+/-
+
COS
(FDAC)
Ϭ2
SPI INTERFACE &
CONTROL REGISTERS
P R E S CA LE R
PHASE DETEC-
TOR & VCO
I D_I A_DC_AC
GADINAC
I_OUT
OFFSDEATC
Q DAC
I_OUT
DIFF.
REFCLK
*Half-Band Filters also can be configured for " Zero-Stuffing Only"
PLL CLOCK MULTIPLIER
AND CLOCK DIVIDER
REV. PrA
BLOCK DIAGRAM
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reliable. However, no responsibility is assumed by Analog Devices for its ^{One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.}
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which may result from its use. No license is granted by implication or Fax: [phone]
© Analog Devices, Inc., 2000
otherwise under any patent or patent rights of Analog Devices.
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