AD9736_15 Datasheet, PDF (1/72 Pages) Analog Devices – 10-/12-/14-Bit, 1200 MSPS DACS

10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
FEATURES
Pin-compatible family
Excellent dynamic performance
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
LVDS sampling integrity
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
160-lead chip scale ball grid array (CSP_BGA) package
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 μm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
S1 S2 S3
DACCLK– DACCLK+
SDIO
SDO
CSB
SCLK
DATACLK_OUT+
DATACLK_OUT–
C1
SPI
CONTROLLER C2
C3
C3
CLOCK
DISTRIBUTION
S3
DATACLK_IN+
DATACLK_IN–
DB[13:0]+
DB[13:0]–
2×
14-, 12-,
IOUTA
10-BIT DAC
CORE
IOUTB
C2
BAND GAP
C1S1
REFERENCE
CURRENT _S2
VREF
I120
Figure 1.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2. Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
3. Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
4. Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5. The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
Rev. A
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