AD9674 Datasheet, PDF (1/2 Pages) Analog Devices – Octal Ultrasound AFE with Digital Demodulator

Data Sheet
Octal Ultrasound AFE
with Digital Demodulator
AD9674
FEATURES
GENERAL DESCRIPTION
8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
The AD9674 is designed for low cost, low power, small size, and
Low power: 150 mW per channel, TGC mode, 40 MSPS;
ease of use for medical ultrasound. It contains eight channels of a
65 mW per channel, CW mode; <30 mW at power-up
VGA with an LNA, a CW harmonic rejection I/Q demodulator
Time gain compensation (TGC) channel input-referred noise:
0.8 nV/√Hz, maximum gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Low noise preamplifier (LNA)
Input-referred noise voltage: 0.78 nV/√Hz, gain = 21.6 dB
Programmable gain: 15.6 dB/17.9 dB/21.6 dB
0.1 dB compression: 1.00 V p-p/0.75 V p-p/0.45 V p-p
Flexible active input impedance matching
Variable gain amplifier (VGA)
Attenuator range: 45 dB, linear-in-dB gain control
Postamp gain: 21 dB/24 dB/27 dB/30 dB
Antialiasing filter (AAF)
with programmable phase rotation, an AAF, an ADC, a digital
HPF, and RF decimation by 2.
Each channel features a maximum gain of up to 52 dB, a fully
differential signal path, and an active input preamplifier termination.
The channel is optimized for high dynamic performance and
low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the serial port interface (SPI). Assuming a 15 MHz noise
bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is
94 dB. In CW doppler mode, each LNA output drives an I/Q
demodulator that has independently programmable phase
rotation with 16 phase settings.
Programmable second-order low-pass filter (LPF) from 8 MHz
to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter (HPF)
Analog-to-digital converter (ADC)
Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS
Configurable serial low voltage differential signaling (LVDS)
Continuous wave (CW) doppler mode harmonic rejection I/Q
demodulator
Individual programmable phase rotation
Dynamic range per channel: >160 dBFS/√Hz
Close-in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input
RF digital HPF and decimation by 2
Power-down of individual channels is supported to increase battery
life for portable applications. Standby mode allows quick power-up
for power cycling. In CW doppler operation, the VGA, AAF, and
ADC are powered down. The ADC contains several features
designed to maximize flexibility and minimize system cost, such as
a programmable clock, data alignment, and programmable digital
test pattern generation. The digital test patterns include built-in
fixed patterns, built-in pseudorandom patterns, and custom
user-defined test patterns entered via the serial port interface.
This product is protected by a U.S. patent.
10 mm × 10 mm, 144-ball CSP_BGA
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DVDD
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
CWD I/Q
DEMODULATOR
VGA
AAF
14-BIT
ADC
FILTER/
DECIMATOR
SERIALIZER LVDS
CWQ+
CWQ–
CWI+
CWI–
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
8 CHANNELS
NCO
SERIAL
PORT
INTERFACE
AD9674
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
For more information about the AD9674, contact Analog Devices, Inc., at [e-mail].
Rev. Sp0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com