AD9656BCPZ-125 Datasheet, PDF (1/44 Pages) Analog Devices – Quad, 16-Bit, 125 MSPS, JESD204B 1.8 V Analog-to-Digital Converter

Data Sheet
Quad, 16-Bit, 125 MSPS, JESD204B
1.8 V Analog-to-Digital Converter
AD9656
FEATURES
SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V)
SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V)
SFDR = 86 dBc to Nyquist (VREF = 1.4 V)
JESD204B Subclass 1 coded serial digital outputs
Flexible analog input range: 2.0 V p-p to 2.8 V p-p
1.8 V supply operation
Low power: 197 mW per channel at 125 MSPS (two lanes)
DNL = ±0.6 LSB (VREF = 1.4 V)
INL = ±4.5 LSB (VREF = 1.4 V)
650 MHz analog input bandwidth, full power
Serial port control
Full chip and individual channel power-down modes
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Standby mode
APPLICATIONS
Medical imaging
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Portable test equipment
GENERAL DESCRIPTION
The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 125 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
Individual channel power-down is supported and typically
consumes less than 14 mW when all channels are disabled. The
ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable output
clock, data alignment, and digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN DVDD DRVDD
VINA+
VINA–
VINB+
VINB–
RBIAS
VREF
SENSE
AGND
VINC+
VINC–
VIND+
VIND–
16
PIPELINE
ADC
16
PIPELINE
ADC
JESD204B
INTERFACE
REF
SELECT
1V
TO
1.4V
HIGH
SPEED
SERIALIZERS
16
PIPELINE
ADC
16
PIPELINE
ADC
CONTROL
REGISTERS
CML TX
OUTPUTS
VCM
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
AD9656
SERDOUT0+
SERDOUT0–
SERDOUT1+
SERDOUT1–
SERDOUT2+
SERDOUT2–
SERDOUT3+
SERDOUT3–
DSYNC+
DSYNC–
Figure 1.
The AD9656 is available in an RoHS-compliant, nonmagnetic,
56-lead LFCSP.
It is specified over the −40°C to +85°C industrial temperature
range. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. It has a small footprint. Four ADCs are contained in a small, 8
mm × 8 mm package.
2. An on-chip phase-locked loop (PLL) allows users to provide
a single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
3. The configurable JESD204B output block supports up to
6.4 Gbps per lane.
4. JESD204B output block supports one, two, and four lane
configurations.
5. Low power of 198 mW per channel at 125 MSPS, two lanes.
6. The SPI control offers a wide range of flexible features to
meet specific system requirements.
Rev. 0
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