AD9643_17 Datasheet, PDF (1/36 Pages) Analog Devices – 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Data Sheet
14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V
Dual Analog-to-Digital Converter (ADC)
AD9643
FEATURES
SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
−151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 785 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9643 is a dual, 14-bit analog-to-digital converter (ADC)
with sampling speeds of up to 250 MSPS. The AD9643 is designed
to support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the two external
14-bit LVDS output ports and formatted as either interleaved or
channel multiplexed.
Flexible power-down options allow significant power savings,
when desired.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+A
VIN–A
VCM
VIN+B
VIN–B
PIPELINE
14-BIT 14
ADC
AD9643
PARALLEL
DDR LVDS
PIPELINE
14-BIT 14
ADC
AND
DRIVERS
REFERENCE
SERIAL PORT
1 TO 8
CLOCK
DIVIDER
D0±_.
.
...
D13±
DCO±
OR±
OEB
PDWN
NOTES
SCLK SDIO CSB
CLK+ CLK– SYNC
1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9643 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
2. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
4. SYNC input allows synchronization of multiple devices.
5. 3-pin, 1.8 V SPI port for register programming and register
readback.
6. Pin compatibility with the AD9613, allowing a simple
migration down from 14 bits to 12 bits. This part is also pin
compatible with the AD6649 and the AD6643.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com