AD9639BCPZ-170 Datasheet, PDF (1/36 Pages) Analog Devices – Quad, 12-Bit, 170 MSPS/210 MSPS Serial Output 1.8 V ADC

Data Sheet
Quad, 12-Bit, 170 MSPS/210 MSPS
Serial Output 1.8 V ADC
AD9639
FEATURES
4 ADCs in one package
JESD204 coded serial digital outputs
On-chip temperature sensor
−95 dB channel-to-channel crosstalk
SNR: 65 dBFS with AIN = 85 MHz at 210 MSPS
SFDR: 77 dBc with AIN = 85 MHz at 210 MSPS
Excellent linearity
DNL: ±0.28 LSB (typical)
INL: ±0.7 LSB (typical)
780 MHz full power analog bandwidth
Power dissipation: 325 mW per channel at 210 MSPS
1.25 V p-p input voltage range, adjustable up to 1.5 V p-p
1.8 V supply operation
Clock duty cycle stabilizer
Serial port interface features
Power-down modes
Digital test pattern enable
Programmable header
Programmable pin functions (PGMx, PDWN)
APPLICATIONS
Communication receivers
Cable head end equipment/M-CMTS
Broadband radios
Wireless infrastructure transceivers
Radar/military-aerospace subsystems
Test equipment
GENERAL DESCRIPTION
The AD9639 is a quad, 12-bit, 210 MSPS analog-to-digital con-
verter (ADC) with an on-chip temperature sensor and a high
speed serial interface. It is designed to support the digitizing
of high frequency, wide dynamic range signals with an input
bandwidth of up to 780 MHz. The output data is serialized
and presented in packet format, consisting of channel-specific
information, coded samples, and error code correction.
The ADC requires a single 1.8 V power supply. The input clock
can be driven differentially with a sine wave, LVPECL, CMOS,
or LVDS. A clock duty cycle stabilizer allows high performance
at full speed with a wide range of clock duty cycles. The on-chip
reference eliminates the need for external decoupling and can
be adjusted by means of SPI control.
Various power-down and standby modes are supported. The
ADC typically consumes 150 mW per channel with the digital
link still in operation when standby operation is enabled.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VCM A
VIN + B
VIN – B
VCM B
VIN + C
VIN – C
VCM C
VIN + D
VIN – D
VCM D
RBIAS
TEMPOUT
AD9639
BUF SHA
PIPELINE
ADC
12
DOUT + A
CHANNEL A
DOUT – A
BUF SHA
PIPELINE
ADC
12
DOUT + B
CHANNEL B
DOUT – B
BUF SHA
PIPELINE
ADC
12
DOUT + C
CHANNEL C
DOUT – C
BUF SHA
PIPELINE
ADC
12
DOUT + D
CHANNEL D
DOUT – D
REFERENCE
SERIAL
PORT
DATA RATE
MULTIPLIER
PGM3
PGM2
PGM1
PGM0
RESET
SCLK SDI/ SDO CSB CLK+ CLK–
SDIO
Figure 1.
Fabricated on an advanced CMOS process, the AD9639 is avail-
able in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. An on-chip PLL allows users to provide a single ADC
sampling clock; the PLL distributes and multiplies up to
produce the corresponding data rate clock.
3. The JESD204 coded data rate supports up to 4.2 Gbps
per channel.
4. The AD9639 operates from a single 1.8 V power supply.
5. Flexible synchronization schemes and programmable
mode pins are available.
6. An on-chip temperature sensor is included.
Rev. B
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