AD9634 Datasheet, PDF (1/32 Pages) Analog Devices – 12-Bit, 170 MSPS/210 MSPS/250 MSPS

12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
AD9634
FEATURES
SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 87 dBc at 185 MHz AIN and 250 MSPS
−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 350 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The AD9634 is designed to
support communications applications where low cost, small size,
wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit
LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+
VIN–
VCM
PIPELINE 12
12-BIT
ADC
PARALLEL
AD9634
DDR LVDS
AND
DRIVERS
REFERENCE
SERIAL PORT
1-TO-8
CLOCK DIVIDER
D0±_./D1±
.
.
D10±/D11±
DCO±
OR±
SCLK SDIO CSB
CLK+ CLK–
Figure 1.
Programming for setup and control is accomplished using a
3-wire, SPI-compatible serial interface.
The AD9634 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This product
is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4. 3-pin, 1.8 V SPI port for register programming and readback.
5. Pin compatibility with the AD9642, allowing a simple
migration up to 14 bits, and with the AD6672.
Rev. 0
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