AD9625_17 Datasheet, PDF (1/74 Pages) Analog Devices – 1.3 V/2.5 V Analog-to-Digital Converter

Data Sheet
12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
1.3 V/2.5 V Analog-to-Digital Converter
AD9625
FEATURES
12-bit 2.5 GSPS ADC, no missing codes
SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
Differential analog input: 1.2 V p-p
Differential clock input
3.2 GHz analog input bandwidth, full power
High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS
Subclass 1: 6.5 Gbps at 2.6 GSPS
Two independent decimate by 8 or decimate by 16 filters
with 10-bit NCOs
Supply voltages: 1.3 V, 2.5 V
Serial port control
Flexible digital output modes
Built-in selectable digital test patterns
Timestamp feature
Conversion error rate < 10^−15
APPLICATIONS
Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures
GENERAL DESCRIPTION
The AD9625 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) that operates at conversion rates of up to
2.6 giga samples per second (GSPS). This product is designed
for sampling wide bandwidth analog signals up to the second
Nyquist zone. The combination of wide input bandwidth, high
sampling rate, and excellent linearity of the AD9625 is ideally
suited for spectrum analyzers, data acquisition systems, and a
wide assortment of military electronics applications, such as
radar and electronic countermeasures.
The analog input, clock, and SYSREF± signals are differential
inputs. The JESD204B-based high speed serialized output is
configurable in a variety of one-, two-, four-, six-, or eight-lane
configurations. The product is specified over the industrial
temperature range of −40°C to +85°C, measured at the case.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD DRGND
VCM
VIN+
VIN–
RBIAS_EXT
REFERENCE
ADC
CORE
DIGITAL INTERFACE
AND CONTROL
DDC
f_S/8 OR f_S/16
CONTROL
REGISTERS
SYSREF±
CLK±
CLOCK
MANAGEMENT
AD9625
CMOS DIGITAL
INPUT/OUTPUT
CMOS
DIGITAL
INPUT/
OUTPUT
LVDS
DIGITAL
INPUT/
OUTPUT
SERDOUT[0]±
SERDOUT[1]±
SERDOUT[2]±
SERDOUT[3]±
SERDOUT[4]±
SERDOUT[5]±
SERDOUT[6]±
SERDOUT[7]±
FD
RSTB
IRQ
SYNCINB±
DIVCLK±
SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. High performance: exceptional SFDR in high sample rate
applications, direct RF sampling, and on-chip reference.
2. Flexible digital data output formats based on the JESD204B
specification.
3. Control path SPI interface port that supports various
product features and functions, such as data formatting,
gain, and offset calibration values.
Rev. C
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