AD9572 Datasheet, PDF (1/20 Pages) Analog Devices – Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Fiber Channel/Ethernet Clock Generator IC,
PLL Core, Dividers, 7 Clock Outputs
AD9572
FEATURES
Fully integrated dual VCO/PLL cores
167 fs rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz
178 fs rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
418 fs rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,
100 MHz, 125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filters
Copy of reference clock output
Rates configured via strapping pins
Space saving, 6 mm × 6 mm, 40-lead LFCSP
0.71 W power dissipation (LVDS operation)
1.07 W power dissipation (LVPECL operation)
3.3 V operation
APPLICATIONS
Fiber channel line cards, switches, and routers
Gigabit Ethernet/PCIe support included
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
REFSEL
REFCLK
XTAL
OSC
LDO
VCO
CMOS
1 × 25MHz
LVPECL
OR LVDS
2 × 106.25MHz
AD9572
LDO
VCO
LVPECL
OR LVDS
LVPECL
OR LVDS
1 × 156.25MHz
2 × 100MHz
OR 125MHz
CMOS
1 × 33.33MHz
FORCE_LOW
FREQSEL
Figure 1.
GENERAL DESCRIPTION
The AD9572 provides a multioutput clock generator function
along with two on-chip PLL cores, optimized for fiber channel
line card applications that include an Ethernet interface. The
integer-N PLL design is based on the Analog Devices, Inc.,
proven portfolio of high performance, low jitter frequency
synthesizers to maximize network performance. Other applica-
tions with demanding phase noise and jitter requirements also
benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference. Each output
divider and feedback divider ratio is preprogrammed for the
required output rates.
A second PLL also operates as an integer-N synthesizer and
drives two LVPECL or LVDS output buffers for 106.25 MHz
operation. No external loop filter components are required, thus
conserving valuable design time and board space.
The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame
chip scale package (LFCSP) and can be operated from a single
3.3 V supply. The temperature range is −40°C to +85°C.
10G SFP+
CPU
ISLAND
16-PORT FIBRE CHANNEL ASIC
1 × 156.25MHz
2 × 106.25MHz
1 × 100MHz/125MHz
1 × 25MHz
1 × 33.33MHz
AD9572
QUAD SFP QUAD SFP QUAD SFP QUAD SFP
PHY
PHY
PHY
PHY
Figure 2. Typical Application
Rev. 0
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