AD9548 Datasheet, PDF (1/112 Pages) Analog Devices – Quad/Octal Input Network Clock Generator/Synchronizer

Quad/Octal Input Network Clock
Generator/Synchronizer
AD9548
FEATURES
APPLICATIONS
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
4 pairs of reference input pins with each pair configurable as
a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
30-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
88-lead LFCSP package
Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9548 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9548 generates an output clock synchronized to one of up to
four differential or eight single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9548
continuously generates a clean (low jitter), valid output clock
even when all references have failed by means of a digitally
controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of
−40°C to +85°C.
STABLE
SOURCE
FUNCTIONAL BLOCK DIAGRAM
ANALOG
FILTER
CLOCK
MULTIPLIER
AD9548
REFERENCE INPUTS
AND
MONITOR MUX
DIGITAL
PLL
DAC
SYNC
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CHANNEL 2
DIVIDER
CHANNEL 3
DIVIDER
SERIAL CONTROL INTERFACE
(SPI or I²C)
EEPROM
STATUS AND
CONTROL PINS
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
www.analog.com
Fax: [phone]
©2009 Analog Devices, Inc. All rights reserved.