AD9540 Datasheet, PDF (1/32 Pages) Analog Devices – 655 MHz Low Jitter Clock Generator

655 MHz Low Jitter Clock Generator
AD9540
FEATURES
APPLICATIONS
Excellent intrinsic jitter performance
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase fre-
quency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable internal clock rates
Programmable edge delay with 93 fS resolution
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP package
Programmable charge pump current (up to 4 mA)
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND VCML VCP
CP_RSET
REFIN
REFIN
SYNC_IN/STATUS
CLK1
CLK1
SCLK
SDI/O
SDO
CS
S2
S1
S0
SYNC, PLL
LOCK
M DIVIDER
N DIVIDER
PHASE
FREQUENCY
DETECTOR
CP
REF, AMP
CHARGE
PUMP
DIVIDER
1, 2, 4, 8
SERIAL
CONTROL
PORT
TIMING AND
CONTROL LOGIC
PHASE/
FREQUENCY
PROFILES
CML
CLK
DIVCLK
48
14
DDS ¹⁰
DAC
CP
CLK2
CLK2
DRV_RSET
OUT0
OUT0
VCML
IOUT
IOUT
Figure 1.
DAC_RSET
Rev. 0
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