AD9500 Datasheet, PDF (1/11 Pages) Analog Devices – Digitally Programmable Delay Generator

a
Digitally Programmable
Delay Generator
AD9500
FEATURES
10 ps Delay Resolution
2.5 ns to 10 ␮s Full-Scale Range
Fully Differential Inputs
Separate Trigger and Reset Inputs
Low Power Dissipation—310 mW
MIL-STD-883 Compliant Versions Available
APPLICATIONS
ATE
Pulse Deskewing
Arbitrary Waveform Generators
High Stability Timing Source
Multiple Phase Clock Generators
GENERAL DESCRIPTION
The AD9500 is a digitally programmable delay generator, which
provides programmed delays, selected through an 8-bit digital
code, in resolutions as small as 10 ps. The AD9500 is con-
structed in a high performance bipolar process, designed to
provide high speed operation for both digital and analog circuits.
The AD9500 employs differential TRIGGER and RESET
inputs which are designed primarily for ECL signal levels but
function with analog and TTL input levels. An onboard ECL
reference midpoint allows both of the inputs to be driven by
either single ended or differential ECL circuits. The AD9500
output is a complementary ECL stage, which also provides a Q
R
parallel output circuit to facilitate reset timing implementations.
The digital control data is passed to the AD9500 through a
transparent latch controlled by the LATCH ENABLE signal. In
the transparent mode, the internal DAC of the AD9500 will
attempt to follow changes at the inputs. The LATCH ENABLE
is otherwise used to strobe the digital data into the AD9500
latches.
The AD9500 is available as an industrial temperature range
device, –25°C to +85°C, and as an extended temperature range
device, –55°C to +125°C. Both grades are packaged in a 24-lead
cerdip (0.3" package width), as well as 28-leaded and leadless
surface mount packages. The AD9500 is available in versions
compliant with MIL-STD-883. Refer to the Analog Devices
Military Products Databook or current AD9500/883B data
sheet for detailed specifications.
FUNCTIONAL BLOCK DIAGRAM
TRIGGER
TRIGGER
RESET
RESET
DIFFERENTIAL
ANALOG
INPUT
STAGE
+V_S
C_EXT
C_S
ECL COMMON
AD9500
TIMING
CONTROL
CIRCUIT
Q
ECL_REF
R_S
R_SET
–V_S
ECL
VOLTAGE
Q
REFERENCE
INTERNAL DAC
REFERENCE
Q_R
CURRENT
TTL LATCHES
–V_S GROUND D₀ D₁ D₂ D₃ D₄ D₅ D₆ D₇ LATCH OFFSET
(LSB)
(MSB) ^{ENABLE ADJUST}
PIN CONFIGURATIONS
D₄ 1
D_{5 2}
D_{6 3}
D₇ (MSB) 4
ECL_REF 5
OFFSET ADJUST 6
C_S 7
+V_S 8
TRIGGER 9
TRIGGER 10
RESET 11
RESET 12
AD9500
TOP VIEW
(Not to Scale)
24 D₃
23 D₂
22 D₁
21 D₀ (LSB)
20 LATCH ENABLE
19 GROUND
18 R_S
17 –V_S
16 ECL COMMON
15 Q_R
14 ^Q
13 Q
4 3 2 1 28 27 26
D₇ (MSB) 5
ECL_REF 6
OFFSET ADJUST 7
NC 8
C_S 9
+V_S 10
TRIGGER 11
AD9500
TOP VIEW
(Not to Scale)
25 D₀ (LSB)
24 LATCH ENABLE
23 GROUND
22 NC
21 R_S
20 –V_S
19 ECL COMMON
12 13 14 15 16 17 18
REV. D
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© Analog Devices, Inc., 1999