AD9444_15 Datasheet, PDF (1/40 Pages) Analog Devices – 14-Bit, 80 MSPS, A/D Converter

FEATURES
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical
1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
644) or CMOS-compatible and include the means to reduce
the overall current needed for short trace distances.
14-Bit, 80 MSPS, A/D Converter
AD9444
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
AD9444
VIN+
VIN–
BUFFER
T/H
CLK+
CLK–
CLOCK
AND TIMING
MANAGEMENT
14
PIPELINE
CMOS
2
ADC
OR
LVDS ²⁸
OUTPUT
STAGING
2
REF
DFS
DCS MODE
OUTPUT MODE
OR
D13–D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
Rev. 0
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