AD9430 Datasheet, PDF (1/20 Pages) Analog Devices – 12-Bit, 170 MSPS 3.3V A/D Converter

PRELIMINARY TECHNICAL DATA
a
12-Bit, 170 MSPS
3.3V A/D Converter
Preliminary Technical Data
AD9430
FEATURES
SNR = 65dB @ Fin up to 65MHz at 170Msps
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs)
SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs)
Excellent Linearity:
- DNL = +/- 1 lsb (typ)
- INL = +/- 1.5 lsb (typ)
Two Output Data options
- Demultiplexed 3.3V CMOS outputs each at 85 Msps
- LVDS at 170Msps
700 MHz Full Power Analog Bandwidth
On–chip reference and track/hol d
Power dissipation = 1.25W typical at 170Msps
1.5V Input voltage range
+3.3V Supply Operation
Output data format option
Data Sync input and Data Clock output provided
Interleaved or parallel data output option (CMOS)
Clock Duty Cycle Stabilizer.
APPLICATIONS
Wireless and Wired Broadband Communications
- Wideband carrier frequency systems
- Cable Reverse Path
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization
PRODUCT DESCRIPTION
The AD9430 is a 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and
is optimized for low cost, low power, small size and ease of
use. The product operates up to 170 Msps conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier systems.
The ADC requires a +3.3V power supply and a differential
encode clock for full performance operation. No external
reference or driver components are required for many
applications. The digital outputs are TTL/CMOS or LVDS
compatible. Separate output power supply pins support
interfacing with 3.3V CMOS logic.
An output data format select option of two’s complement or
offset binary is supported. In CMOS mode two output buses
support demultiplexed data up to 85 Msps rates. A data sync
input is supported for proper output data port alignment and
a data clock output is available for proper output data timing.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100 pin surface mount plastic package (100
TQFP ePAD) specified over the industrial temperature range
(–40°C to +85°C).
SENSE
VREF
AGND DrGND
DrV_DD AV_DD
AD9430
Scaleable
Reference
AIN+
AIN-
DS+
DS-
Track &
Hold
ADC
12-bit
Pipeline
Core
LVDS
Outputs
Data(24), OR(2)
12
A port
Data(12), OR(1)
CMOS
Outputs
B port
Data(12), OR(1)
ENC+
ENC-
Clock
Management
Select CMOS or LVDS
DCO+
DCO-
REV. PrG 4/01/2002
S1
S2
S4
S5
AD9430 FUNCTIONAL BLOCK DIAGRAM
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© Analog Devices, Inc., 2002