AD9229-65EBZ Datasheet, PDF (1/40 Pages) Analog Devices – Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter

FEATURES
Four ADCs in 1 package
Serial LVDS digital output data rates
to 780 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 69.5 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
400 MHz full power analog bandwidth
Power dissipation
1,350 mW at 65 MSPS
985 mW at 50 MSPS
1 V p-p to 2 V p-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
APPLICATIONS
Digital beam-forming systems for ultrasound
Wireless and wired broadband communications
Communication test equipment
GENERAL DESCRIPTION
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance in applications
where a small package size is critical.
The ADC requires a single 3 V power supply and TTL-/CMOS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported and typically consumes 3 mW when enabled.
Fabricated with an advanced CMOS process, the AD9229 is
available in a Pb-free, 48-lead LFCSP package. It is specified
over the industrial temperature range of –40°C to +85°C.
Quad, 12-Bit, 50/65 MSPS,
Serial, LVDS, 3 V A/D Converter
AD9229
VIN+A
VIN–A
VIN+B
VIN–B
VIN+C
VIN–C
VIN+D
VIN–D
FUNCTIONAL BLOCK DIAGRAM
PDWN DTP
DRVDD DRGND
AD9229
SHA
PIPELINE ^{12 SERIAL}
ADC
LVDS
D+A
D–A
SHA
PIPELINE ^{12 SERIAL}
ADC
LVDS
D+B
D–B
SHA
PIPELINE ^{12 SERIAL}
ADC
LVDS
D+C
D–C
SHA
PIPELINE ^{12 SERIAL}
ADC
LVDS
D+D
D–D
VREF
SENSE
REFT
REFB
REF
SELECT
0.5V
DATA RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
AGND LVDSBIAS
CLK
Figure 1.
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. A data clock out (DCO) is provided, which operates up to
390 MHz and supports double-data rate operation (DDR).
3. The outputs of each ADC are serialized LVDS with data
rates up to 780 Mbps (12 bits × 65 MSPS).
4. The AD9229 operates from a single 3.0 V power supply.
5. Packaged in a Pb-free, 48-lead LFCSP package.
6. The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
Rev. B
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