AD892E_15 Datasheet, PDF (1/2 Pages) Analog Devices – 30 MB PEAK DETECTORS

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30 Mb/sPeakDetectors
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AD892E/AD892TI
FEATURES
FUNCTIONAL BLOCK DIAGRAM
30 Mb/s Data Transfer Rate Capability (AD892E)
25 Mb/s Data Transfer Rate Capability (AD892T)
1 ns (max) Additional Pulse Pairing
Two Versions
Differential ECl Data Output (AD892E)
TIl Data Output (AD892T)
Variable Gain Amplifier with 30 dB max Gain and
AGC
LEVEl. SET
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AD81I2EJAD892T
AMP
COMP
OBSOLETE 40dBControl Range
Two Gain of 4 RF Buffers with 200 n Differential-load
Drive Capability
0.2 dB/ms Typical Gain Drift in Hold Mode
1 ...S AGC Attack/Decay Times Using a 1000 pF
External Capacitor
Dynamic Input Clamp Ensures Fast Recovery after
Write to Read Transients
Two Matched Offset Trimmed Comparators
One-Shot Pulse Width Set Using External Resistor
Operates from +5 V and +12 V Supplies
PRODUCT DESCRIPTION
The AD892E1AD892T is a complete subsystem for recovering
binary information from differentiating channels with transfer
rates up to 30 megabits per second. It is connected to the oUt-
vaA
INPUT
va.
ou11'UT
VGA
LEVELSET
eUFF 1
INPUT
REeT,
OUTPUT
REcr 2
OUTPUT
REcr 3
OUTPUT
RECT
INPUT
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The AD892E/AD892T provides both level and time-domain
qualification. Level qualification is performed on half cycles of
the rectified data waveform using a user-defined threshold level
which is applied to the level qualification comparator. The out-
put of the head amplifier and performs the signal conditioning
put of this comparator drives the data inpUt of a master. slave
and the data qualification task with a minimum of external
components.
flip-flop. A second, matched comparator detects zero-crossings
and clocks the flip-flop. Each valid zero-crossing causes a time-
The AD892E/AD892T has the flexibility to perform both con-
tinuous and sampled AGC functions; it is also ideal for embed-
ded, dedicated, or mixed servo applications. Fast acquisition
and low droop while in the hold mode allows for the AGC oper-
ation to be performed within the sector header withoUt compro-
mising channel behavior when reading data. Two user-defined
filter/equalizer stages may be employed, thus allowing maximum
design flexibility. This greatly simplifies the design of the over-
all channel characteristics.
domain filter one-shot to generate a pulse with a user-defined
period. During the one-shot period the flip-flop is disabled, pre-
venting the detection of additional zero-crossing events. This
technique prevents single-bit errors from being propagated into
two-bit errors. The zero-crossing event also triggers an output
one-shot, again with a user defined pulse width. For maximum
flexibility, the data output is a Schortky open-collector transistor
with a separate digital ground to minimize digital feedthrough
(AD892T) or differential ECL (AD892E).
Three low offset, 50 MHz full-wave rectifiers are provided. One
rectifier drives the internal sample-and-hold circuitry; this signal
is available to the user to set the attack and decay characteris-
tics of the sample and hold. The other two rectifier outpUts are
The AD892E1AD892T is available in a 44-pin plastic leaded
chip carrier (PLCC) and is specified to operate over the com-
mercial (0 to + 70cC) temperature range.
provided to generate the qualification level and to feed the single-
ended passive differentiator. The threshold setting and differen-
tiation is performed by an external RLC network.
This is an abridged version of the data sheet. To obtain a complete data
sheet, contact your nearest sales office.
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